module WriteMemory(address, counter, data, mem_addr, mem_data);
input [1:0] counter;
input [31:0] address;
input [31:0] data;

output [31:0] mem_addr;
output reg [15:0] mem_data;

wire is_align;

assign is_align = !address[0];
assign mem_addr = address >> 1;


always @(*) begin
	if(is_align) begin
		if(counter == 0) begin
			mem_data <= data[15:0];
		end else begin
			mem_data <= data[31:16];
		end
	end else begin
		if(counter == 0) begin
			mem_data <= {data[7:0],8'bx};
		end else if(counter == 1) begin
			mem_data <= data[23:8];
		end else begin
			mem_data <= {8'bx,data[31:24]};
		end
	end
end

endmodule